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Platform uses silicon wafer itself as the package and introduces a highly integrated approach to power system design across automotive, industrial, and AI data center markets
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Summary: onsemi today unveiled the Embedded Power Platform (EPP), redefining system power delivery through unprecedented power density and integration of multiple dies into a single silicon device. By jointly optimizing electrical, mechanical and thermal performance within a single architecture, EPP enables up to 3 – 5x higher power density compared with current solutions with a highly integrated approach to power system design. This helps customers reduce complexity while scaling for the increasing demands of AI infrastructure and electrification.
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SCOTTSDALE, Ariz., Sept. 16, 2026 (GLOBE NEWSWIRE) — onsemi today unveiled the Embedded Power Platform (EPP), a breakthrough architecture that uses the silicon wafer itself as the foundation of the package and introduces a highly integrated approach to power system design. Designed as a scalable platform, EPP brings electrical, mechanical and thermal design together from the outset to help customers achieve higher power density, improve system performance and accelerate development in AI, electrification and autonomous applications.
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“For decades, the semiconductor and the package have been treated as separate technologies. EPP changes that by making the silicon itself part of the system architecture,” said Hassane El-Khoury, President and CEO of onsemi. “EPP brings together advanced semiconductor technologies, manufacturing and system-level optimization into a common architecture that can evolve alongside future innovations. This approach can redefine how power systems are built and create a new foundation for AI infrastructure, electrification and automation.”
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What’s New: EPP reimagines the package from passive housing into an active contributor to system performance. By using the silicon wafer itself as the package, EPP enables the seamless integration and interconnection of silicon, silicon carbide (SiC) and gallium nitride (GaN) technologies within a highly integrated wafer-level architecture. Multiple devices, including FETs, drivers and controllers, can be embedded together in a single package and co-optimized for electrical, thermal and mechanical performance. This enables complete power-system co-design, allowing electrical, thermal and mechanical characteristics to be evaluated and optimized together from day one. The result is higher power density, improved system performance, reduced development complexity and faster time-to-market.
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EPP also leverages onsemi’s standard 12-inch silicon wafer manufacturing capabilities, bringing key integration processes into the precision and control of the semiconductor fab. This applies mature semiconductor design tools, wafer-level manufacturing and advanced simulation capabilities to power-system integration, helping improve performance while accelerating innovation.
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